When I add the encrypted file as source files I get the following error.
Analysis Results
sources_1[#UNDEF] Badly-written IEEE-1735 file '/tmp/temp/counter_e.v' cannot be decrypted ["/tmp/temp/counter_e.v":]
[#UNDEF] Badly-written IEEE-1735 file '/tmp/temp/counter_e.v' cannot be decrypted ["/tmp/temp/counter_e.v":]
[#UNDEF] Badly-written IEEE-1735 file '/tmp/temp/counter_e.v' cannot be decrypted ["/tmp/temp/counter_tb.v":]
[#UNDEF] Badly-written IEEE-1735 file 'counter_e.v' cannot be decrypted ["/tmp/temp/counter_tb.v":]
sim_1[#UNDEF] Badly-written IEEE-1735 file '/tmp/temp/counter_e.v' cannot be decrypted ["/tmp/temp/counter_e.v":]
[#UNDEF] Badly-written IEEE-1735 file '/tmp/temp/counter_e.v' cannot be decrypted ["/tmp/temp/counter_e.v":]
[#UNDEF] Badly-written IEEE-1735 file '/tmp/temp/counter_e.v' cannot be decrypted ["/tmp/temp/counter_tb.v":]
[#UNDEF] Badly-written IEEE-1735 file 'counter_e.v' cannot be decrypted ["/tmp/temp/counter_tb.v":]
My encrypted Verilog design file looks
`pragma protect begin_protected
`pragma protect version=2
`pragma protect encrypt_agent="ipecrypt"
`pragma protect encrypt_agent_info="https://ipencrypter.com Version: 18.3.00"
`pragma protect author="A"
`pragma protect author_info="AI"
`pragma protect data_method="aes128-cbc"
`pragma protect begin_toolblock
`pragma protect rights_digest_method="sha256"
`pragma protect key_keyowner="Xilinx"
`pragma protect key_keyname="xilinxt_2017_05"
`pragma protect key_method="rsa"
`pragma protect key_block
...
This can be addressed by adding an empty common block in you IP and re-encrypt it.
`pragma protect version=2
`pragma protect author="A", author_info="AI"
`pragma protect data_method="aes128-cbc"
`pragma protect begin_commonblock
`pragma protect end_commonblock
`pragma protect begin_toolblock
`pragma protect rights_digest_method="sha256"
`pragma protect key_keyowner = "Xilinx"
`pragma protect key_keyname= "xilinxt_2017_05"
`pragma protect key_method = "rsa"
`pragma protect key_public_key
...
